During the manufacture of a semiconductor device it is usually necessary to etch contact holes through an insulating dielectric layer of the device down to the underlying active or passive elements of the device. The etching of the contact holes creates vias in the dielectric layer. Metal is then placed in the vias. The metal filled vias are used to connect the underlying active or passive elements of the semiconductor device to external leads.
The bottom layer in a semiconductor device will usually be made of salicide, silicon or polysilicon. The process of etching contact holes through an overlying dielectric layer requires high etch selectivity between the dielectric layer and the bottom layer. This is due to the contact height difference between various elements of the semiconductor device. For example, the contact height for a gate of a semiconductor transistor will be different than the contact height for the source/drain of the semiconductor device. High etch selectivity between the dielectric layer and the bottom layer is especially required for devices that have additional structures at a polysilicon level (e.g., polysilicon capacitors).
Reactive ion etch (RIE) lag is a well-known phenomenon that causes the etch rate of a contact etch hole to decrease as the etch process continues to etch the contact etch hole deeper and deeper. The aspect ratio of a contact etch hole is the ratio of its depth to its width. As a contact etch hole is etched deeper and deeper, the aspect ratio increases. In RIE lag the magnitude of the decrease in etch rate is proportional to the increase in magnitude of the aspect ratio. In prior art methods the presence of RIE lag is undesirable. Therefore prior art methods are directed toward the minimization of RIE lag.
Prior art methods sometimes provide contact etch selectivity by using stop etch layers such as salicide or silicon oxynitride (SiON). A stop etch layer is placed at a desired depth where the contact etch process is to end. The etch process stops when the etch process reaches the stop etch layer. The stop etch layer prevents overetch and breakthrough when the etch process etches down to the underlying active element of the semiconductor device. A stop etch layer is usually a few hundred Angstroms thick. An Angstrom is one tenth of a nanometer. (1 Å=10−10 m).
Consider a prior art etch process that etches each of a plurality of contact etch holes to a different depth in a dielectric layer. Each of the contact etch holes have the same diameter and therefore are etched at the same rate. After the first contact etch hole (i.e., the shallowest contact etch hole) reaches its underlying stop etch layer, the etch process continues. In the time period during which the prior art etch process is etching the second contact etch hole (i.e., the next shallowest contact etch hole) down to its desired depth, the prior art etch process in the first contact etch hole is laterally etching the sides of the first contact etch hole. The presence of stop etch layer at the bottom of the first contact etch hole laterally channels the prior art etch process to etch the sides of the first contact etch hole. The prior art etch process therefore causes the first contact etch hole to have a final diameter that is larger than desired.
To solve this problem and to correct other similar deficiencies in prior art methods, there is a need in the art for an improved system and method for providing contact etch selectivity when contact etch holes are etched through a dielectric layer in a semiconductor device.